In a typical block of computer memory, memory cells are arranged in rows and columns, where the memory cells in each row are accessed by energizing a word line shared by those memory cells, where each different row has its own unique word line and each word line has its own unique address in the memory block.
For example, for a block of computer memory having 64 rows of memory cells, each of the 64 different word lines would typically have its own unique 6-bit address. A particular row of memory cells is accessed by applying the 6-bit address of the row's corresponding word line to an address decoder that is connected to all 64 word lines. The address decoder decodes (i.e., interprets) the 6-bit address and energizes the corresponding word line. In typical memory blocks, at most one word line is energized at a time.
FIG. 1 shows a schematic block diagram of a portion of a conventional address decoder 100 for decoding a 6-bit word-line address to energize one of 64 word lines in a block of computer memory. FIG. 1 shows 2-bit decoder 102 and word-line driver 104. Two-bit decoder 102 receives bit A0 and bit A1 as well as clock signal CK and generates four decoded bit values DEC0-DEC4, which are applied to the Y<3:0> input of word-line driver 104. Word-line driver 104 also receives two other decoded bit values DEC74 and DEC118 (at its Y118 and Y118 inputs, respectively) as well as enable signal ENABLE (at its EN input) and generates four word-line drive signals WL<3:0> that are applied to four of the 64 word lines in the memory block. In this example, A0 and A1 are two of the six bits (e.g., the two least significant bits (LSBs)) in the 6-bit word-line address (A5 A4 A3 A2 A1 A0) used to access one of the rows in the memory block.
The components of conventional address decoder 100 that are not shown in FIG. 1 include:    A 2-bit decoder, similar to 2-bit decoder 102, that converts word-line address bits A2 and A3 into four decoded bit values DEC4-DEC7;    A 2-bit decoder, similar to 2-bit decoder 102, that converts word-line address bits A4 and A5 into four decoded bit values DEC8-DEC11; and    Fifteen other word-line drivers similar to word-line driver 104, each connected to a different set of four word lines in the memory block.In addition to receiving all four decoded bits DEC0-DEC3, each of the 16 different word-line drivers also receives a unique 2-bit combination of one of decoded bits DEC4-DEC7 and one of decoded bits DEC8-11, where each different 2-bit combination corresponds to a different set of four word lines in the memory block.
As shown in FIG. 1, 2-bit decoder 102 includes two edge-triggered flip-flops AFF0 and AFF1 and four logical-AND gates AND0-AND3. Flip-flop AFF0 receives address bit A0 at its data input D and clock CK at its clock input CK and presents, at each rising edge of clock CK, the current value of bit A0 at its output Q as signal AL0 and an inverted version of the current value of bit A0 at its output QN as signal ALN0. Similarly, flip-flop AFF1 receives address bit A1 at its data input D and clock CK at its clock input CK and presents, at each rising edge of clock CK, the current value of bit A1 at its output Q as signal AL1 and an inverted version of the current value of bit A1 at its output QN as signal ALN1.
Each AND gate ANDi generates a different decoded bit value DECi by applying the logical AND operation to its two inputs A and B. Table I illustrates the processing implemented by 2-bit decoder 102 for the four different possible combinations of values for bits A0 and A1. This table indicates that a different one (and only one) of DEC1-DEC4 is 1 for each different combination of A0 and A1.
TABLE I2-BIT DECODER PROCESSINGA1A0AL1ALN1AL0ALN0DEC0DEC1DEC2DEC30001010001010110010010100100101110101000
FIG. 2 shows a schematic diagram of a portion of a conventional word-line driver BA, which may be used to implement word-line driver 104 and each of the 15 other word-line drivers in address decoder 100 of FIG. 1. In particular, FIG. 2 shows that portion of word-line driver BA responsible for controlling two of the four word lines (labeled WL0 and WL1) controlled by word-line driver BA based on the values of decoded bits Y0, Y1, Y74, and Y118. Not shown in FIG. 2 is a similar portion responsible for controlling the remaining two word lines controlled by word-line driver BA based on the values of decoded bits Y2, Y3, Y74, and Y118.
Assuming that Y74 and Y118 are both high (i.e., logical value 1), then the circuitry of FIG. 2 will cause (1) word-line drive signal WL0 to be high (i.e., thereby energizing word line WL0), if both Y0 and EN are both high and (2) word-line drive signal WL1 to be high (i.e., thereby energizing word line WL1), if both Y1 and EN are both high. Note that the signals W0 and W1 are inverted at the inputs of the corresponding AND gates.
The purpose of the enable signal EN is to ensure that all of the processing to the left of the final AND gates in FIG. 2 (including the processing of the 2-bit decoders, such as decoder 102 of FIG. 1) has settled before any word-line drive signal is generated, in order to prevent two or more word lines from being driven at the same time.
FIG. 3 shows a timing diagram illustrating the timing of the processing of the circuitry shown in FIGS. 1 and 2. Time line A* indicates the time that it takes to set up and apply the various word-line address bits Ai to the D inputs of the various flip-flops (e.g., A0 to input D of AFF0 in FIG. 1) prior to the rising edge of clock CK, illustrated in time line CK. Time line AL* indicates the time that it takes for the flip-flops to generate their output values ALi and ALNi. Time line DEC* indicates the time that it takes for the AND gates in FIG. 1 to generate their output values DECi. Time line W* indicates the time that it takes for the transistors shown in FIG. 2 to generate and apply the input values Wi to the AND gates in FIG. 2.
Time line ENABLE indicates that the enable signal is not asserted until all of the previous processing has settled, and time line WL indicates the total delay from the rising edge of clock CK until the corresponding word-line drive signal WLi goes high (including the time that it takes the AND gates in FIG. 2 to generate their outputs). Note that the ENABLE signal is delayed an additional amount to provide a safety margin to account for process, voltage, and temperature (PVT) variations.
The provision and use of the ENABLE signal increases the power consumption and layout area, while reducing the speed of the resulting address decoder circuitry.